Commun. Comput. Phys.,
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Volume 3.


RLC Equivalent Circuit Synthesis Method for Structure-Preserved Reduced-Order Model of Interconnect in VLSI

Fan Yang 1, Xuan Zeng 1*, Yangfeng Su 2, Dian Zhou 3

1 State Key Lab. of ASIC & System, Microelectronics Department, Fudan University, Zhangheng Road 825, Shanghai 201203, China.
2 Mathematics Department, Fudan University, Han Dan Road 220, Shanghai 200433, China.
3 State Key Lab. of ASIC & System, Microelectronics Department, Fudan University, Zhangheng Road 825, Shanghai 201203, China; and E.E. Department, University of Texas at Dallas, Richardson, TX 75080, USA.

Received 12 February 2007; Accepted (in revised version) 25 July 2007
Available online 8 October 2007

Abstract

This paper aims to explore RLC equivalent circuit synthesis method for reduced-order models of interconnect circuits obtained by Krylov subspace based model order reduction (MOR) methods. To guarantee pure RLC equivalent circuits can be synthesized, both the structures of input and output incidence matrices and the block structure of the circuit matrices should be preserved in the reduced-order models. Block structure preserving MOR methods have been well established. In this paper, we propose an embeddable \emph{I}nput-\emph{O}utput structure \emph{P}reserving \emph{O}rder \emph{R}eduction (IOPOR) technique to further preserve the structures of input and output incidence matrices. By combining block structure preserving MOR methods and IOPOR technique, we develop an RLC equivalent circuit synthesis method \emph{RLCSYN} (RLC SYNthesis). Inline diagonalization and regularization techniques are specifically proposed to enhance the robustness of inductance synthesis. The pure RLC model, high modeling accuracy, passivity guaranteed property and SPICE simulation robustness make \emph{RLCSYN} more applicable in interconnect analysis, either for digital IC design or mixed signal IC simulation.

AMS subject classifications: 94C05, 93A15, 68U07, 68U20, 41A21

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Key words: Interconnect circuit, model order reduction, equivalent circuit synthesis.

*Corresponding author.
Email: yangfan@fudan.edu.cn (F. Yang), xzeng@fudan.edu.cn (X. Zeng), yfsu@fudan.edu.cn (Y. Su), zhoud@fudan.edu.cn (D. Zhou)
 

The Global Science Journal